Today's multi chip modules (MCM's) in power applications face significant challenges in terms of heat dissipation and heat management. Coupled with the need to dissipate heat in a uniform manner with low thermal impedance, there is also a need to reduce space and cost. Traditional approaches to packaging MCM's have been in the form of a Land Grid Array (LGA) or Ball Grid Array (BGA) type substrate, which consist of multiple chips (semiconductor dice) plus passive components placed on a laminate substrate. The substrate material conventionally has a high-thermal impedance and, even with enhanced via technology for heat management, still falls short of the low thermal impedance of a lead frame design.
A conventional lead frame device has excellent thermal conductance and optimum heat dissipation with regard to the power component mounting surfaces. But, a conventional lead frame design and manufacturing process limits its ability to have multiple passive components mounted within the package. Manufacturing a lead frame that is adapted to receive a power semiconductor die and passive components is often associated with long manufacturing times, increased expenses, and is generally not considered an efficient manufacturing option. Conventional lead frames are adapted to receive only power semiconductor dice. Thus, external components must be coupled to the lead frame to ensure operational effectiveness, which also adds to both the cost (of procurement, placement, etc.) and the space of the customer's board.
FIGS. 1A-1B illustrate a conventional lead frame package 10. The lead frame includes a semiconductor die pad 14 and multiple leads 16 arranged about the periphery of the lead frame 10. A conventional method for producing the leadless semiconductor chip package shown in FIGS. 1A-1B comprises the steps of: (1) attaching a semiconductor chip 12 onto the die pad 14 of a lead frame 10, wherein the lead frame 10 comprises a plurality of leads 16 arranged about the periphery of the die pad 14; (2) wire-bonding the leads of the lead frame 10 to bonding pads on the semiconductor chip (shown as wires 18 in FIG. 1b); and (3) forming a package body 20 over the semiconductor chip 12 and the lead frame 10 in a manner that each lead 16 of the lead frame 10 has at least a portion 17 exposed from the bottom of the package body. This conventional lead frame package 10 only supports a single semiconductor chip 12. The package 10 cannot support any passive components. Thus, the passive components (e.g., resistors and capacitors) are necessarily external to the package 10.